This invention relates generally to computer memory, and more particularly to providing a configurable command sequence for a memory interface device.
Contemporary high performance computing main memory systems are generally composed of one or more dynamic random access memory (DRAM) devices, which are connected to one or more processors via one or more memory control elements. Overall computer system performance is affected by each of the key elements of the computer structure, including the performance/structure of the processor(s), any memory cache(s), the input/output (I/O) subsystem(s), the efficiency of the memory control function(s), the main memory device(s), and the type and structure of the memory interconnect interface(s).
Extensive research and development efforts are invested by the industry, on an ongoing basis, to create improved and/or innovative solutions to maximizing overall system performance and density by improving the memory system/subsystem design and/or structure. High-availability systems present further challenges as related to overall system reliability due to customer expectations that new computer systems will markedly surpass existing systems in regard to mean-time-between-failure (MTBF), in addition to offering additional functions, increased performance, increased storage, lower operating costs, etc. Other frequent customer requirements further exacerbate the memory system design challenges, and include such items as ease of upgrade and reduced system environmental impact (such as space, power and cooling).
FIG. 1 relates to U.S. Pat. No. 5,513,135 to Dell et al., of common assignment herewith, and depicts an early synchronous memory module. The memory module depicted in FIG. 1 is a dual in-line memory module (DIMM). This module is composed of synchronous DRAMs 8, buffer devices 12, an optimized pinout, and an interconnect and capacitive decoupling method to facilitate high performance operation. The patent also describes the use of clock re-drive on the module, using such devices as phase-locked loops (PLLs).
FIG. 2 relates to U.S. Pat. No. 6,173,382 to Dell et al., of common assignment herewith, and depicts a computer system 210 which includes a synchronous memory module 220 that is directly (i.e. point-to-point) connected to a memory controller 214 via a bus 240, and which further includes logic circuitry 224 (such as an application specific integrated circuit, or “ASIC”) that buffers, registers or otherwise acts on the address, data and control information that is received from the memory controller 214. The memory module 220 can be programmed to operate in a plurality of selectable or programmable modes by way of an independent bus, such as an inter-integrated circuit (I2C) control bus 234, either as part of the memory initialization process or during normal operation. When utilized in applications requiring more than a single memory module connected directly to a memory controller, the patent notes that the resulting stubs can be minimized through the use of field-effect transistor (FET) switches to electrically disconnect modules from the bus.
Relative to U.S. Pat. Nos. 5,513,135, 6,173,382 further demonstrates the capability of integrating all of the defined functions (address, command, data, presence detect, etc) into a single device. The integration of functions is a common industry practice that is enabled by technology improvements and, in this case, enables additional module density and/or functionality.
FIG. 3, from U.S. Pat. No. 6,510,100 to Grundon et al., of common assignment herewith, depicts a simplified diagram and description of a memory system 310 that includes up to four registered DIMMs 340 on a traditional multi-drop stub bus. The subsystem includes a memory controller 320, an external clock buffer 330, registered DIMMs 340, an address bus 350, a control bus 360 and a data bus 370 with terminators 395 on the address bus 350 and the data bus 370. Although only a single memory channel is shown in FIG. 3, systems produced with these modules often included more than one discrete memory channel from the memory controller, with each of the memory channels operated singly (when a single channel was populated with modules) or in parallel (when two or more channels where populated with modules) to achieve the desired system functionality and/or performance.
FIG. 4, from U.S. Pat. No. 6,587,912 to Bonella et al., depicts a synchronous memory module 410 and system structure in which the repeater hubs 420 include local re-drive of the address, command and data to the local memory devices 401 and 402 via buses 421 and 422; generation of a local clock (as described in other figures and the patent text); and the re-driving of the appropriate memory interface signals to the next module or component in the system via bus 400.
FIG. 5 depicts a contemporary system composed of an integrated processor chip 500, which contains one or more processor elements and an integrated memory controller 510. In the configuration depicted in FIG. 5, multiple independent cascade interconnected memory interface busses 506 are logically aggregated together to operate in unison to support a single independent access request at a higher bandwidth with data and error detection/correction information distributed or “striped” across the parallel busses and associated devices. The memory controller 510 attaches to four narrow/high speed point-to-point memory busses 506, with each bus 506 connecting one of the several unique memory controller interface channels to a cascade interconnect memory subsystem 503 (or memory module) which includes at least a hub device 504 and one or more memory devices 509. Some systems further enable operations when a subset of the memory busses 506 are populated with memory subsystems 503. In this case, the one or more populated memory busses 508 may operate in unison to support a single access request.
FIG. 6 depicts a memory structure with cascaded memory modules 503 and unidirectional busses 506. One of the functions provided by the hub devices 504 in the memory modules 503 in the cascade structure is a re-drive function to send signals on the unidirectional busses 506 to other memory modules 503 or to the memory controller 510. FIG. 6 includes the memory controller 510 and four memory modules 503, on each of two memory busses 506 (a downstream memory bus with 24 wires and an upstream memory bus with 25 wires), connected to the memory controller 510 in either a direct or cascaded manner. The memory module 503 next to the memory controller 510 is connected to the memory controller 510 in a direct manner. The other memory modules 503 are connected to the memory controller 510 in a cascaded manner. Although not shown in this figure, the memory controller 510 may be integrated in the processor 500 and may connect to more than one memory bus 506 as depicted in FIG. 5.
As described above, in many high-speed, high capacity memory applications, a memory interface device (MID), often in the form of a “buffer” or “hub device,” is utilized as an interface between one or more high speed busses and one or more memory storage devices. In contemporary systems, the MID and/or memory device functionality can be verified or tested via one or more means. These testing means include, but are not limited to: the execution of normal memory read/writes (e.g. normal operation), the execution of MID or memory device test patterns/sequences under the direction of a memory controller, and the execution of hard-coded test patterns/sequences via internal BIST (built-in-self-test circuitry). Operation of available memory device BIST circuitry, however, requires that the memory device (e.g., DRAM) be initialized to an active state, which may not be possible in the presence of some initial MID faults.
Another challenge associated with the testing and fault determination in a complex, high speed memory system is the need to execute specific commands and command sequences in response to a specific system configuration (e.g. MID/memory device/speed/density) and/or a fault type. Testing may include the need to place the memory system and/or a specific memory subsystem (e.g. a memory module) into one or more specific states, often with the intent to create a “scope loop” condition such that an oscilloscope or network analyzer can be used to determine if signal integrity, timing or other out-of spec interface conditions exist that affect system operability.
High speed daisy-chained memory structures present additional difficulties, due to the need to train multiple interfaces (e.g. drivers, receivers, data capture circuitry, etc) between each driving and receiving device. In this case, a test environment and/or a scope loop may be desired such that one MID can be established as a local ‘master’ device for the purpose of communicating with other MIDs that are downstream. In this case, the ‘master’ device (which may be the first, second or ‘nth’ MID in the daisy chain structure) would be configured to drive and/or receive information on the one or more high speed link connections, and be able to instruct downstream devices to issue commands. In addition to other benefits, this operability would reduce the real-time demands on the memory controller, allowing the system to implement parallel operations.
With the continued integration of BIST operability in emerging devices, the need exists, in advanced high reliability memory systems, to verify the operability of the integrated BIST functions. To do so, it is necessary to test the failure detection and recovery mechanisms of the MID, memory array, or other BIST engine(s)/exerciser routines sourced from such devices as the memory controller or processor (MC/uP). In some cases, prior to and/or during BIST operation it may be required to overwrite valid data locations in the memory array(s) with invalid data. The exercisers/BIST engines would then be started and/or re-started to verify that the engines are able to detect locations with invalid data.
Known solutions to problems such as those listed above, generally involve hard coding test routines (which may include DRAM initialization sequences, as well as write and read operations) into the hub chip hardware state machines, and/or using an intelligent driver chip like the MC/uP, which is designed to communicate with the memory subsystem for the performance of these tasks. It is desirable to perform these tasks, in a situation-dependent manner, without the need for a processing device (e.g. an MC/uP) to directly control the operation, or in at least some instances, without the need to be connected to the MID at all.